1. Field of the Invention
The present invention relates to a semiconductor memory device including a sense amplifier that senses and amplifies potential differences between paired bit lines. Particularly, the invention relates to a sense power supply structure for stably driving a sense amplifier even under a low supply voltage condition.
2. Description of the Background Art
With advances in integration degree of semiconductor memory devices, there arise the problems such as increase in power consumption, and reduction in break down voltage characteristics of the components due to miniaturization. To overcome these problems, a method of reducing an operational power voltage has been developed. For example, an insulating film forming a capacitor of a memory cell in a dynamic random access memory (DRAM) is miniaturized to be a significantly thin film. In view of reliability, potential difference to be applied across the insulating film needs to be reduced, and the method to reduce the operational power voltage is adopted as a countermeasure against such situation. Recently, the reduction in operational power voltage is remarkably progressed. On the other hand, the reduction in the operational power voltage is in a reverse technical direction in view of improvement in the operational characteristics such as sensing operation margin and speed.
FIG. 1 is a circuit diagram of a conventional semiconductor memory device, and particularly shows a configuration of a DRAM memory array. In the memory array, memory cells MC are arranged in rows and columns, word lines WL are disposed corresponding to respective rows of the memory cells MC, and the pairs of bit lines BL and ZBL are disposed corresponding to the respective columns of the memory cells MC. FIG. 1 depicts a configuration of a portion related to a single pair of bit lines BL and ZBL.
The memory cell MC includes a capacitor CM for storing data and an access transistor TRM for connecting the capacitor to the bit line BL in response to a potential on the corresponding word line WL. The access transistor TRM is formed of an n-channel MOS (insulated gate type field effect) transistor. The memory cell capacitor CM receives a predetermined cell-plate voltage Vcp on one electrode node (cell plate node), and stores charge corresponding to stored data on the other electrode SN (storage node). The memory cell MC is connected to one of the corresponding bit lines BL and ZBL, and is shown to be connected to the bit line BL in FIG. 1.
Corresponding to the pair of bit lines BL and ZBL, a sense amplifier SA and an bit-line equalize circuit EQ are provided. The sense amplifier SA senses and amplifies memory cell data. The bit line equalize circuit EQ precharges and equalizes the bit lines BL and ZBL to a predetermined potential in a standby state.
The sense amplifier SA includes cross-coupled p-channel MOS transistors SAP1 and SAP2 (sense transistors), and cross-coupled n-channel MOS transistors SAN1 and SAN2. The sense amplifier SA senses and amplifies a potential difference generated between the bit lines BL and ZBL when made active.
The sense transistor SAP1 is connected between the bit line BL and a node NP, and has the gate connected to the bit line ZBL. The sense transistor SAP2 is connected between the bit line ZBL and the node NP, and its gate is connected to the bit line BL. The sense transistor SAN1 is connected between the bit line BL and a node NN, and its gate is connected to the bit line ZBL. The sense transistor SAN2 is connected between the bit line ZBL and the node NN, and its gate is connected to the bit line BL.
The sense amplifier SA is activated when a sense amplifier driving p-channel MOS transistor SDP and a sense amplifier driving n-channel MOS transistor SDN are each made conductive. The sense amplifier driving n-channel MOS transistor SDN is rendered conductive, in response to activation of a sense amplifier activating signal S0N, to electrically connect the source node NN of the sense transistors SAN1 and SAN2 to a sense power feed line VSL that feeds a ground potential GND. The sense amplifier driving transistor SDP is made conductive in response to activation of a sense amplifier activating signal ZS0P, and electrically connects the source node NP of the sense p-channel MOS transistors SAP1 and SAP2 to a power feed line VSH for transmitting a memory array power supply potential Vdds when made conductive.
A circuit formed including the sense amplifier SA, sense amplifier driving transistor SDN, and sense amplifier driving transistor SDP is hereinbelow referred to as a xe2x80x9csense amplifier/drive circuit SADxe2x80x9d.
The bit line equalize circuit EQ precharges and equalizes the bit lines BL and ZBL to an equalization potential Vbl according to an equalizing signal on an equalizing signal line BLEQ. The bit line equalize circuit includes a precharging transistor for transmitting the equalization potential Vbl to the bit lines, and an equalizing transistor for electrically short-circuiting the bit lines BL and ZBL with each other.
The power feed line VSH, which feeds the sense power voltage Vdds (memory array power supply potential), is connected to an internal voltage down converting circuit VDC. The voltage down converting circuit VDC down-converts an external power potential extVdd, and provides a sense amplifier driving power source at the memory array power potential Vdds.
FIG. 2 is a timing chart representing the operation of the sense amplifier SA shown in FIG. 1. Before a time T01, specifically, before the word line WL is selected to rise in potential, both the bit line BL and bit line ZBL are precharged to a precharge or equalization potential Vbl. Here, the precharge potential Vbl is assumed to be Vdds/2, or the intermediate potential of the memory array power potential Vdds and the ground potential GND. Also, the memory cell MC is assumed to store H data (logical high level data).
At time T01, the word line WL rises in potential, the H data stored in the memory cell MC is read out onto the bit line BL, and a very small potential difference dV is produced between the bit lines BL and ZBL.
At time T02, the levels of the sense amplifier activating signals S0N and ZS0P become H and L levels, respectively; and the sense amplifier SA is activated. Through a sensing operation of the sense amplifier SA, the very small potential difference dV caused between the bit lines BL and ZBL is sensed and amplified. In this operation, since the access transistor TRM in the memory cell MC is conductive, the potential Vdds of the higher potential power feed line VSH is applied through the bit line BL and the transistor TRM to the storage node SN, which is one electrode of the capacitor CM in the memory cell MC.
Here, a threshold voltage of each of the n-channel MOS transistors SAN1 and SAN2 is represented by Vthn, and a threshold voltage of each of the p-channel MOS transistors SAP1 and SAP2 is represented by Vthp.
For the sense amplifier SA to start sensing operation at time T02, gate to source potentials Vgs of the sense transistors SAN1, SAN2, SAP1, and SAP2 must be greater in absolute value than the threshold voltages Vthn and Vthp. When the very small potential difference dV between the bit lines BL and ZBL is disregarded, the following relationship is satisfied before the sensing operation:
Vgs=Vbl=1/2xc3x97Vdds.
When the following relationship holds, the sense amplifier SA securely starts sensing operation:
Vdds greater than max{2xc3x97Vthn, 2xc3x97|Vthp|}.
When the following relationship holds, the sense amplifier SA does not start the sensing operation:
Vdds less than min{2xc3x97Vthn, 2xc3x97|Vthp|}.
In addition, one of the values of Vgsxe2x88x92Vthn and Vgsxe2x88x92|Vthp| significantly influences an initial speed of the sensing operation of the sense amplifier SA. When one of the values of Vgsxe2x88x92Vthn and Vgsxe2x88x92|Vthp| is reduced due to a reduction in the potential Vdds of the higher potential sense amplifier driving power feed line VSH, there is caused an increase in sense time, or a reduction in operation speed of the sense amplifier, and also shortage in sense operation margin against variations in the threshold voltages Vthn and Vthp of the transistors due to variations in processing.
In addition, as shown in FIG. 2, the potentials of the power feed lines VSH and VSL vary according to charging/discharging of the bit lines in sensing operation. Immediately after the start of a sensing operation of the sense amplifier SA at time T03, the potentials of the power feed lines VSH and VSL greatly vary according to charging/discharging of the bit lines BL and ZBL due to the sensing operation of sense amplifier SA. Particularly, the degree of the variation in the potential of the higher potential power feed line VSH, that is, the degree of reduction in the potential thereof, depends on factors, such as a resistance and capacitance of interconnection line of the higher potential power feed line VSH, and the speed of response to potential variation of the voltage down converting circuit VDC. In addition, in conjunction with an increase in potential of the lower potential power feed line VSL, such potential variation would cause significant reduction in the operation speed of the sense amplifier SA, and would eventually cause a malfunction.
An overdriving scheme is proposed to solve the problem, as described above, of shortage in sensing operation margin that is caused due to the reduction in potential of a higher potential power feed line for feeding the higher potential power potential to the sense amplifier SA. An example of the overdriving scheme is disclosed in Japanese Patent Laying-Open Nos. 11-250665 (1999) and 6-215571 (1994); and 1999 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 123 to 124.
FIG. 3 shows a configuration of a circuit for feeding a power potential to a higher potential power feed line of a sense amplifier in an overdriving scheme disclosed, for example, in the above described Japanese Patent Laying-Open No. 11-250655 (1999). Referring to FIG. 3, in order to feed the power supply voltage VSH to the sense amplifier driving circuit SAD, there are provided a voltage down converting circuit 40a for generating a down converted voltage from an external power supply voltage extVdd onto a high level power feed line VSH, and a precharging p-channel MOS transistor P1 for feeding a potential Vddp on an internal power node to the high level power feed line VSH when rendered conductive. The precharging transistor P1 is selectively rendered conductive in response to a signal output by an inverter 45 which in turn receives a precharge signal PRE representing an inactivation of row related circuitry for inversion. The power feed line VSH is connected with a decoupling capacitor Cd.
The voltage down converting circuit 40a includes a reference potential generator circuit 41a for generating two reference potentials Vrefp and Vrefs, a selector 42, a shifter 43, a comparison circuit 44a, and a p-channel transistor P0. The selector 42 selects the reference potential Vrefp as a reference potential Vref when the precharge signal PRE is at an H level, while selects the reference potential Vrefs as the reference potential Vref when the precharge signal PRE is at an L level. The shifter 43 shifts the reference potential Vref selected by the selector 42 and the potential of the high level power feed line VSH. The comparison circuit 44a compares the potential applied through the shifter 43 on the power feed line VSH and the reference potential Vref selected by the selector 42. The p-channel transistor P0 is connected between a node of the external power potential extVdd and the high level power feed line VSH, and receives an output of the comparison circuit 44a on a gate thereof. The shifter 43 is provided for optimizing the operating point of the comparison circuit 44a to increase the gain of the comparison circuit 44a. 
FIG. 4 is a timing chart representing operation of the circuit that feeds the power potential to the higher potential power feed line for driving the sense amplifier according to the overdriving scheme as shown in FIG. 3. In FIG. 4, GND represents a ground potential; Vddp represents a power potential mainly for a peripheral circuit including a control circuit in a DRAM; Vdds represents a power potential mainly for a memory array and sense amplifier circuit; and Vpp represents boosted potential used as, for example, a word line driving potential. These potentials satisfy the the relationship of GND less than Vdds less than Vddp less than Vpp. Hereinafter, Vdds is referred to as a memory array power potential, and Vddp is referred to as a peripheral circuit power potential. The two reference potentials generated from the reference potential generator circuit 40a satisfy the relationships of Vrefp=Vddp and Vrefs=Vdds.
In the standby state, that is, before time T10, the precharge signal PRE is at an H level. Accordingly, out of the reference potentials Vrefp and Vrefs generated from reference potential generator circuit 41a, the selector 42 shown in FIG. 3 selects the reference potential Vrefp as the reference potential Vref. The comparison circuit 44a receives the reference potential Vrefp and the potential of the power feed line VSH through the shifter 43, compares the received two potentials, and adjusts a gate potential of the p-channel transistor P0 so as to equalize the received two potentials to each other. The p-channel transistor P0 has a conductance thereof according to its gate potential, to feed charge from the node of the external power potential extVdd to the high level power feed line VSH.
The precharging p-channel transistor P1 becomes conductive, according to an output signal of the inverter 45 that receives the precharge signal PRE, to feed charge from the node of the peripheral circuit power potential Vddp to the power feed line VSH. According to the charge from the p-channel transistor P0 and the precharging p-channel MOS transistor P1, the power feed line VSH and the decoupling capacitor Cd are charged to the peripheral circuit power potential Vddp.
At time T10, the precharge signal PRE falls to an L level. Responsively, the selector 42 in the voltage down converting circuit 40a selects the reference potential Vrefs to switch the reference potential Vref from the reference potential Vrefp to the reference potential Vrefs. On the other hand, the precharging p-channel transistor P1 receives an H-level signal on its gate, and is responsively driven to a nonconductive state. That is, at this time, feeding of charge from the node of the peripheral circuit power potential Vddp to the power feed line VSH and the decoupling capacitor Cd is stopped.
At time T11, a word line WL is selected, and the potential thereof starts to rise up to the level of the boosted potential Vpp. Responsively, the access transistor TRM of a memory cell MC is rendered conductive, charge retained in the memory cell MC is transferred to a bit line BL, and a very small potential difference dV is caused between bit lines BL and ZBL.
At time T12, sense amplifier activating signals ZS0P and S0N are each activated, and a sense amplifier SA senses and amplifies the very small potential difference dV, which has been generated between the bit lines BL and ZBL. The capacitance value of the decoupling capacitor Cd is pre-set such that charge required for charging the bit line BL that swings to H data (=Vdds) is compensated for by charge pre-accumulated in the decoupling capacitor Cd. Thus, after the amplification by the sense amplifier SA, the potential of the bit line BL and the potential of the power feed line VSH can be made equal to memory array power potential Vdds. When the potential of the power feed line VSH is reduced to or below the memory array power potential Vdds, the voltage down converting circuit 40a operates to feed charge to maintain the potential of the power feed line VSH at the level of memory array power potential Vdds.
The conventional semiconductor memory device shown in FIG. 3 is advantageous in that gate to source potentials Vgs of the p-channel sense transistors SAP1 and SAP2 in the sense amplifier SA are increased from the level of 1/2xc3x97Vdds to the level of the potential Vddpxe2x88x921/2xc3x97Vdds, or increased by the potential of Vddpxe2x88x92Vdds. However, due to a great trend of reduction in operation voltage of the semiconductor memory device, a case may occur where the potential extVdd is equaled to the potential Vddp (extVdd=Vddp). Specifically, a case can occur where the specification value of the external power potential extVdd becomes lower, and there is almost no potential difference between the external power potential extVdd and the peripheral circuit power potential Vddp. Therefore, there is no need to reduce the external power potential extVdd to produce the peripheral circuit power potential Vddp within the semiconductor memory device. In such a case, the source side of the precharging p-channel transistor P1 is configured to be connected to the node of the external power potential extVdd instead of a node of the power potential Vddp internally generated.
FIG. 5 shows a configuration of a circuit for feeding a power potential to a higher potential power feed line for driving the sense amplifier according to the overdriving scheme disclosed in the Japanese Patent Laying-Open No. 1994-215571, as an example of a configuration in which the source of a precharging p-channel transistor is connected to the node of an external power potential extVdd to charge the decoupling capacitor Cd.
Referring to FIG. 5, a power feed line VSH for a sense amplifier/driver circuit SAD is connected with a voltage down converting circuit 40b, a precharging p-channel transistor P2, and the decoupling capacitor Cd. The voltage down converting circuit 40b down converts an external power potential extVdd, to generate a memory array power potential Vdds on the power feed line VSH. The precharging p-channel transistor P2 is connected between the node of the external power potential extVdd and the power feed line VSH, and receives an overdrive instructing signal xcfx86 on its gate.
The voltage down converting circuit 40b includes a reference potential generator circuit 41b, a comparison circuit 44b, and a p-channel transistor P0. The reference potential generator circuit 41b generates a reference potential Vrefs. The comparison circuit 44b compares a potential of the power feed line VSH and the reference potential Vref. The p-channel transistor P0 is connected between the node of the external power potential extVdd and the power feed line VSH, and receives an output of the comparison circuit 44b on its gate.
FIG. 6 is a timing chart representing the operation of the circuit that feeds the power potential to the higher level power feed line for the sense amplifier in the overdriving scheme shown in FIG. 5. In FIG. 6, the represented potentials are assumed to satisfy the relationships similar to those shown in FIG. 4.
Before a time T21, charge is fed from the node of the external power potential extVdd to the power feed line VSH through the p-channel transistor P0 so as to equalize the reference potential Vrefs generated from reference potential generator circuit 41b and the potential of the power feed line VSH to each other. Since the overdriving instructing signal xcfx86 applied to the gate of the precharging p-channel transistor P2 is at an L level, the precharging p-channel transistor P2 is in a conductive state, and charge is also fed to the power feed line VSH from the node of the external power potential extVdd via the precharging p-channel transistor P2. When the potential of the power feed line VSH is increased to or above the memory array power potential, the voltage down converting circuit 40b sets the p-channel transistor P0 to be in a nonconductive state. Therefore, the decoupling capacitor Cd is charged to the potential extVdd by the precharging p-channel transistor P2.
At time T21, a word line WL is selected, and its potential starts to rise up to the level of the boosted voltage Vpp. Charge retained in the memory cell MC is transferred to a bit line BL, and a very small potential difference dV is generated between the bit lines BL and ZBL.
At time T22, sense amplifier activating signals ZS0P and S0N are each activated, and a sense amplifier SA senses and amplifies the very small potential difference dV. Charge required for charging the bit line BL that swings to the H data level (=Vdds) in the sensing operation is compensated for by charge pre-accumulated in the decoupling capacitor Cd. At the time T22, since the overdrive instructing signal xcfx86 is at the L level, charge is continuously fed from the node of the external power potential extVdd to the power feed line VSH and to the decoupling capacitor Cd. Thus, the charge required to charge the bit line BL that swings to the H data level (=Vdds) is directly fed from the node of the external power potential extVdd.
At time T24, the level of the overdrive instructing signal xcfx86 transits to an H level, to turn off the precharging p-channel transistor P2, thereby stopping the supply of charge from the node of the external power potential extVdd to the power feed line VSH and the decoupling capacitor Cd.
When the precharging p-channel transistor P2 stops charging to the power feed line VSH and the decoupling capacitor Cd, the potentials of the power feed line VSH and the bit line BL change to the memory array power potential Vdds according to charging/discharging of the bit lines BL and ZBL.
The period from the time T22 to the time T24 is a so-called initial sensing amplifier operation stage. This initial operation stage is an important stage in which the sensing operation speed and sensitivity of the sensing are determined. Charge is supplemented to the power feed line VSH in the period before the initial stage via the precharging p-channel transistor P2 to intend to improve the sensing operation speed, particularly, in the initial sensing operation stage.
The capacitance value of the decoupling capacitor Cd shown in FIGS. 3 and 5 is predetermined by means of simulation for example, to satisfy the following relationship:
Cdxc3x97(Vdpxe2x88x92Vdds)=Cbaxc3x97Vbl,
where Cba represents a total load amount of all bit lines BL and ZBL subjected to sensing operation, and Vdp represents the precharge potential before starting of the sensing operation of power feed line VSH.
Generally, the potential of an external power supply of a semiconductor memory device is defined by specifications. For example, for a DRAM, the external power supply potential is specified to be in the range of 3.3 Vxc2x10.3 V. When the potential is within the specified range, potential variations of about 10% is permitted to guarantee the operation performance. As shown in FIGS. 3 and 5, the conventional semiconductor memory device is configured such that the decoupling capacitor Cd is charged by the external power source, and as a result, xc2x110% variations in the external power potential lead to xc2x110% variations in the precharge potential of the decoupling capacitor Cd.
As described above, the capacitance value of the decoupling capacitor Cd is set through simulation or the like. However, if the external power potential extVdd varies to a minus side, the precharge potential Vdp is accordingly reduced to cause inadequate charging of the decoupling capacitor Cd. In this case, sufficient gate to source potential Vgs of each of the p-channel sense transistor SAP1 and SAP2 in the sense amplifier SA cannot be secured, thereby causing slow down and margin shortage in the sensing operation. If the external power potential extVdd varies to a plus side, the precharge potential Vdp is increased to cause overcharging to the power feed line VSH and the decoupling capacitor Cd. In this case, since excessive charge is fed to the bit line BL, a problem may arise that the potential fed to the memory cell MC is excessively increased unnecessarily. Specifically, an excessively high potential is applied to an electrode on the side of the bit line BL, i.e., the storage node SN, of the capacitor CM in the memory cell MC, thereby significantly affecting the reliability of the break down voltage characteristics of an insulating film. Particularly, in the configuration shown in FIG. 5, the precharging p-channel transistor P2 is still conductive in the initial sensing/amplifying operation stage, or in the period from the time T22 to the time T24. In this case, there is a significantly high probability that variations in the external power voltage directly influence the insulating film in the memory cell MC.
In the conventional semiconductor memory device configured as described above, the precharge potentials of the higher potential power feed line and the decoupling capacitor are variable according to variations in the predetermined allowable power supply potential. Therefore, if the precharge potential and the capacitance value of the decoupling capacitor are set without taking the variations in the predetermined power supply potential into account, the application of an excessive voltage caused due to the variation in the predetermined power supply potential to the insulating film of the memory cell cannot be prevented.
If the precharge potential and capacitance value of the decoupling capacitor are set so as to assure sufficient sensing operation speed and sensing operation margin with changes of the predetermined power potential to the minus side considered, the possibility is further increased that an excess voltage is applied to the insulating film of the memory cell, which is caused by the changes of the predetermined power supply potential. That is, as the countermeasure against the minus side variation of the external power supply potential, the precharge potential of the power feed line is set higher, or the capacitor value of the decoupling capacitor is made greater. If the predetermined power potential tends to change to the plus side in such condition, an excess charge is supplied to the storage node of the memory via a bit line.
In contrast, when the precharge potential and the capacitance value of the decoupling capacitor are appropriately set to prevent the application of excessive potential to the insulating film of the memory cell, taking the variations to the plus side of the predetermined power potential into account, there would occur shortage in power supply, slow down in sensing operation, shortage in sensing operation margin, and further, reduction in the potential of the power feed line as well. Because of presence of the tolerance for the predetermined power supply potential, a problem arises that it is significantly difficult to determine an appropriate capacitance value of the decoupling capacitor.
It is an object of the present invention to provide a semiconductor memory device that realizes both the speed up of the sensing operation and improvement in the reliability of a memory cell capacitor, coping with reduced power supply voltage level.
Another object of the invention is to provide a semiconductor memory device that allows setting of an appropriate decoupling capacitance value without being influenced by variations in a specification-guaranteed potential of a predetermined power supply.
Still another object of the present invention is to provide a semiconductor memory device capable of performing high speed sensing operation even at a low power supply voltage without impairing the reliability in a memory cell insulating film.
A semiconductor memory device according to an aspect of the present invention includes: a pair of bit lines; a memory cell connected to one of the paired bit lines; a sense amplifier for sensing and amplifying a potential difference of the paired bit lines that is caused in accordance with data read from the memory cell; a first power feed line for feeding a higher potential driving power to the sense amplifier; a second power feed line for feeding a higher potential driving power to the sense amplifier; a first sense amplifier driving transistor connected between the first power feed line and the sense amplifier; a second sense amplifier driving transistor connected between the second power feed line and the sense amplifier; a first decoupling capacitor connected between the first power feed line and a ground potential source; a second decoupling capacitor connected between the second power feed line and the ground potential source; a first power feed circuit for precharging the first power feed line and the first decoupling capacitor to a first potential prior to activation of the sense amplifier; and a second power feed circuit for charging the second power feed line and the second decoupling capacitor to a second potential lower than the first potential.
According to another aspect of the invention, a semiconductor memory device includes: a pair of bit lines; a memory cell connected to one of the bit lines in the pair; a sense amplifier for sensing and amplifying a potential difference of the paired bit lines that is caused in accordance with data read from the memory cell; a power feed line for feeding a higher potential driving power to the sense amplifier; a sense amplifier driving transistor connected between the power feed line and the sense amplifier; constant decoupling capacitor connected between power feed line and a ground potential source with fixed capacitance value; a variable decoupling capacitor connected to the power feed line and having a decoupling capacitance value thereof varied in response to a control signal; a charging circuit for charging the power feed line, the constant decoupling capacitor, and the variable decoupling capacitor from a predetermined power supply; and a monitoring and controlling circuit for monitoring the potential of the predetermined power supply, outputting the control signal according to the result of monitoring, to control the capacitance value of the variable decoupling capacitor.
The two sense amplifier power feed lines mitigate the influence of the potential variation of the predetermined power supply, and implements the sense amplifier operation according to the overdriving scheme to prevent the slow down of the sensing operation at the initial sensing operation stage. In addition, the coupling of the two sense power feed lines mitigates the potential applied to the storage node of a memory cell.
The use of the constant and variable decoupling capacitor can allow an appropriate capacitance value to be set internally to cope with any variation of the predetermined power supply.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.